• CPU configuration

• 1k * 13 bits on chip ROM
• 32 * 8 bits on-chip registers (SRAM, general purpose)
• 5 level stacks for subroutine nesting
• Less than 1.5 mA at 5V/4MHz
• Typically 15 uA at 3V/32kHz
  
• Typically 1 uA during Sleep mode

• I/O port configuration

• 2 bidirectional I/O ports : P5, P6
• 12 I/O pins
• Wake-up port : P6
• 6 Programmable pull-down I/O pins
• 7 programmable pull-high I/O pins
• 7 programmable open-drain I/O pins
• External interrupt : P60

• Operating voltage range(base on 2 clocks):

• 2.1V~5.5V at 0~70°C (commercial)
• 2.3V~5.5V at -40~85°C (industrial)

• Operating frequency range

• Crystal mode:  
  DC ~ 20MHz/2clks @ 5V
  DC ~ 8MHz/2clks @ 3V
  DC ~ 4MHz/2clks @ 2.1V
• IRC mode: 

Internal RC Frequency	Drift Rate
Temperature (-40C~85C)	Voltage	Process	Total
1MHz	∮1%	∮3% @ 2.1~5.5V	∮2%	∮6%
4MHz	∮1%	∮3 @ 2.1~5.5V%	∮2%	∮6%
8MHz	∮1%	∮2% @ 3.0~5.5V	∮2%	∮5%
16MHz	∮1%	∮1% @ 4.0~5.5V	∮2%	∮4%

• ERC mode: DC ~ 2MHz/2clks @ 2.1V

• Peripheral configuration

• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrup
• 2/4 clocks per instruction cycle selected by code option
• High EFT immunity

• Three available interrupts

• TCC overflow interrupt
• Input-port status changed interrupt (wake-up from sleep mode)
• External interrupt

• Special Features

• Programmable free running watchdog timer
• Power saving sleep mode
• Selectable oscillation mode

• Other features

• Programmable prescaler of oscillator set-up time
• One security register to prevent intrusion of user's OTP memory code
• One configuration register to match user's requirement

• Package Type:  

• 14-pin DIP 300mil : EM78P153KD14J
• 14-pin SOP 150mil : EM78P153KSO14J

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