SPC5604CF2MLL6 SPC5604 开发板学习板用32位单片机
飞思卡尔POWERPC SPC5604CF2MLL6 LQFP100 询价为准
SPC5604CF2MLL6 LQFP100
SPC5604B/C Microcontroller Data Sheet
32-bit MCU family built on the Power Architecture™ for
automotive body electronics applications
Features:
• Single issue, 32-bit CPU core complex (e200z0)
— Compliant with the Power Architecture™
embedded category
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. With the optional
encoding of mixed 16-bit and 32-bit
instructions, it is possible to achieve significant
code size footprint reduction.
• Up to 512 Kbytes on-chip flash supported with the
flash controller
• Up to 48 Kbytes on-chip SRAM
• Memory protection unit (MPU) with 8 region
descriptors and 32-byte region granularity
• Interrupt controller (INTC) with 148 interrupt
vectors, including 16 external interrupt sources and
18 external interrupt/wakeup sources
• Frequency modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus
masters
• Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
• Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulation functions (eMIOS-lite)
• 10-bit analog-to-digital converter (ADC)
• 3 serial peripheral interface (DSPI) modules
• Up to 4 serial communication interface (LINFlex)
modules
• Up to 6 enhanced full CAN (FlexCAN) modules
with configurable buffers
• 1 inter IC communication interface (I2C) module
• Up to 123 configurable general purpose pins
supporting input and output operations (package
dependent)
• Real Time Counter (RTC) with clock source from
128 kHz or 16 MHz internal RC oscillator
supporting autonomous wakeup with 1 ms
resolution with max timeout of 2 seconds
• Up to 6 periodic interrupt timers (PIT) with 32-bit
counter resolution
• 1 System Module Timer (STM)
• Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus standard
• Device/board boundary Scan testing supported with
per Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
• On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
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