VREG, BOR, POR

Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip

voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and

space of a second external regulator on an application board. Additionally, internal power-on reset (POR)

and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.

2.8.1

On-chip Voltage Regulator (VREG)

A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors

are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins

to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the

primary concern of the application.

2.8.1.1

Using the On-chip VREG

To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended

operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by

the core logic will be generated by the VREG. Each VDD pin requires on the order of
1.2 μF (minimum)

capacitance for proper regulation of the VREG. These capacitors should be located as close as possible

to the VDD pins