Disabling the On-chip VREG

To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to

the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied

high.

2.8.2

On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit

Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the

burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is

to create a clean reset throughout the device during the entire power-up procedure. The trip point is a

looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device

operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-

up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled

(VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their

respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage

protection circuit will tie XRS low if the VDD rail rises above its trip point. See Section 4 for the various trip

points as well as the delay time for the device to release the XRS pin after the under-voltage or over-

voltage condition is removed. Figure 2-10 shows the VREG, POR, and BOR. To disable both the VDD and

VDDIO BOR functions, a bit is provided in the BORCFG register. See the "Systems Control and Interrupts"

chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18) for

details